1. Field of the Invention
The present invention relates to several processes for fabricating gate structures in a MOS device, and more particularly, for fabricating gate structures having improved gate materials in which the stress and the thermal stability of the improved gate materials are decreased and enhanced respectively.
2. Description of the Prior Art
Metallic silicides have been used as an interconnection material for fabricating semiconductor components in integrated circuits in order to overcome certain inherent disadvantages of polycrystalline silicon. The primary disadvantage of this material is its minimum sheet resistivity that is about 10 ohms per square. Various silicides, materials formed by the reaction of a refractory metal or a near-noble metal with silicon, have been used on the polycrystalline silicon because of the reduced sheet resistance in order to improve the performance of large scaled integrated circuits. The metallic suicides permit the scaling down of interconnects and gate line widths that is required to achieve very large scale integration.
Self-aligned silicide processes or salicide processes are commonly employed to provide a metal silicide layer over the polysilicon gate electrode and over the source/drain regions of the silicon substrate, to facilitate electrically and metallurgically connecting the silicon to metal interconnects. A salicide process normally comprises the following steps: Firstly, a MOS transistor having a gate, source/drain regions, and spacers are formed above a silicon substrate. Secondly, a metallic layer with a thickness of about 200 angstroms to 1000 angstroms is then deposited on the surface of the silicon substrate through a magnetron DC sputtering method. Thirdly, upon application of a high temperature, part of the metallic layer reacts with silicon above the source/drain regions and polysilicon above the gate of the MOS transistor, thereby forming silicide layers. Finally, unreacted residual metal remaining after the reactive process is then removed by a wet etching method, thereby leaving behind the metal silicide layer on the top surfaces of the MOS terminals.
Titanium (Ti) is one of the most commonly used materials for the salicide processes and as a gate material in ULSI technology. Other materials utilized include cobalt (Co), nickel (Ni), platinum (Pt), tungsten (W), molybdenum (Mo), and copper (Cu). FIG. 1 shows a conventional gate structure 10 using titanium silicide as a gate material in ULSI technology. The gate structure comprises a silicon substrate 12 having a gate oxide layer 14 formed thereon. A polysilicon layer 16 is deposited over the gate oxide layer follows by the coating of a barrier layer 18 over the polysilicon layer. Next, the salicide process mentioned before is used to form a titanium silicide layer 20 over the barrier layer. Finally, an anti-reflection film 22 is coated on top of the titanium silicide layer and a capping layer 24 is formed thereon for the purpose of self-aligned contact (SAC) under 0.25 micro technologies.
The titanium silicide layer formed by a conventional salicide process has two basic structures, a metastable C-49 phase titanium silicide (C-49 TiSi.sub.x) structure and a thermodynamically more stable C-54 phase titanium silicide (C-54 TiSi.sub.2) structure having a lower resistance. C-49 phase titanium silicide has a resistance of between about 60 .mu..OMEGA./cm to 90 .mu..OMEGA./cm and a formation temperature of between about 400.degree.C to 500.degree.C. C-54 phase titanium silicide has a lower resistance of between about 14 .mu..OMEGA./cm to 16 .mu..OMEGA./cm, but a rather high formation temperature of between about 700.degree.C to 750.degree.C. In the manufacturing process, generally the higher resistance C-49 phase titanium silicide will be transformed to a lower resistance C-54 phase titanium silicide through the application of a rapid thermal processing (RTP).
The sputtered titanium silicide layer intrinsic high stress characteristic after high temperature RTP is shown in FIG. 2, where a curve of normalized stress against normalized temperature is drawn to show the thermal stress window for titanium silicide. As what is shown, the stress for titanium silicide rises rapidly after been heated above a normalized temperature of about 0.7, and some peeling phenomena can be observed therein. Therefore, something has to be done in order to protect the titanium silicide layer from peeling during or after a high temperature RTP process, thus an alternative process for fabricating a gate structure in ULSI technology is desired.